In modern DRAM's, an address system is employed in which row and column addresses are multiplexed through a set of address terminals in response to a pair of external clocks. The first clock generates a row address strobe (RAS) and a second clock generates a column address strobe (CAS). The benefit of this addressing technique is that the number of lines or terminals employed for address inputs to a chip are reduced by a half, thereby enabling a substantial reduction in required chip real estate for input/output terminals.
During a DRAM read/write cycle, the RAS signal is active for a portion of the time and inactive for another portion of the time. During its active state, it is at a logical low level and during its inactive state, it is at a logical high level. When the RAS signal is in its inactive state, presetting and recharging of the DRAM circuitry is accomplished to ready it for the next memory cycle. During this phase, word lines (i.e., X address lines) are restored from the active state (low logical level) to the standby state (high logical level)--assuming use of P-MOS access transistors for DRAM cells--an internal read-write cycle restores charges to memory cell storage capacitors; address buffers and sense amplifiers are reset; and bit lines are precharged.
DRAMS have seen wide usage in personal computers (PC). When a personal computer's clock is eight or ten mHz, most DRAMS are fast enough to keep up with the PC's central processing unit (CPU). If the CPU clock runs faster, a conventional DRAM is unable to keep up with the CPU's clock rate and system performance is thereby degraded.
In general, CPU performances are best when a memory access is accomplished in two CPU clock cycles. However, other system considerations often require additional clock cycles to be employed for memory accessing. For instance, in personal computers such as the IBM PS/2, a memory access is accomplished in three clock cycles. In such systems, the RAS signal is pulled to the high or inactive state shortly after the commencement of the first clock cycle and is pulled low to the active state at the beginning of the second clock cycle. During the period that the RAS signal is in the inactive state, the DRAM executes the reset/precharge action.
So long as the CPU operates with an eight or ten mHz clock, each clock cycle is, at least, 100 nanoseconds long and there is more than sufficient time to perform the DRAM's reset/precharge functions. However, if a 33 mHz CPU clock is used, then each CPU clock cycle is 30 nanoseconds and, a computer-generated RAS signal allows only approximately 20 nanoseconds for reset/precharge functions. This is inadequate for high speed DRAMS, which require a reset/precharge time of 30 nanoseconds.
To avoid having to redesign the CPU's internal RAS generation functions and circuitry to accommodate a 33 mHz clock, various alternatives exist, none of which are attractive. The first is that a new chip can be designed with a faster reset/precharge time. This would be very difficult to achieve without using a more advanced (and expensive) CMOS technology. Similarly, an internal redesign of the PC could accomplish the same operation, however compatibility problems with other previously designed PC's would be created.
Others have attempted to cope with this problem by employing an extended, on-chip internal precharge cycle which commences upon the rise of the RAS signal from its low (active) to its high (inactive) state. This on-chip-created cycle is implemented by a clock chain and causes an extension of the RAS inactive time, to enable both DRAM resetting and recharging. This implementation, while enabling use of standard CPU-generated RAS signals, utilizes a long timing chain that is triggered by the start of the RAS low to high signal transition. As a result, the timing chain must constantly create a time-out period for the entire RAS reset/precharge time. Timing inaccuracies occur in the timing chain due to variabilities in delay arising from temperature variations, manufacturing anomalies etc. Such an implementation is described by Kobayashi et al. in "A 47ns 64KW by 4b CMOS DRAM With Relaxed Timing Requirements", Proceedings of the 1986 IEEE International Solid-State Circuits Conference, pp. 260, 261, and in "A High Speed 64k by 4 CMOS DRAM Using On-Chip Self-Timing Techniques", IEEE Journal of Solid-State Circuits, Vol. SC-21, No. 5, October, 1986, pp. 655-660.
Other prior art in this area is as follows:
U.S Pat. No. 4,602,356 issued Jul. 22, 1986 to Noyaki et al., entitled "Semiconductor Memory Device", describes a semiconductor memory device that operates under a so called address multiplex access method. A row part of the device is enabled by receiving a row address strobe signal. A column part of the device is enabled by simultaneously receiving both a column address strobe signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the column address strobe signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the row address strobe signal.
U.S. Pat. No. 4,608,666 issued Aug. 26, 1986 to Uchida entitled "Semiconductor Memory", discloses a large capacity and high speed semiconductor memory. Static memory cell rows are provided so as to correspond to dynamic memory cell rows in a dynamic memory cell array. Information is transferred with transfer means between static memory cells in the static memory cell rows and dynamic memory cells corresponding thereto. Access for a read/write operation externally required is effected to static memory cell rows.
U.S. Pat. No. 4,638,462 issued Jan. 20, 1987 to Rajeevakumar et al., entitled "Self-Timed Precharge Circuit", discloses a self-timed precharge circuit for a memory array. The circuit consists of an X-line complement circuit connected to the outputs of a plurality of falling edge detectors, and a precharge generator circuit connected to the output of the X-line complement circuit. Each falling edge detector is connected to a separate wordline of the system memory array. In operation, the precharge generator circuit is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline connected thereto resets.
U.S. Pat. No. 4,636,989 issued Jan. 13, 1987 to Ikuyaki, entitled "Dynamic MOS Random Access Memory", discloses a DRAM which is accessed in response to an address strobe signal, has an automatic refresh circuit which consists of a clock generator that generates refresh clock pulses when the address strobe signal is not produced, and an address counter that increments a refresh address by counting the refresh clock pulses. Information retained in memory cells is automatically refreshed by an operation of the automatic refresh circuit. The DRAM of this arrangement does not need a special external terminal for the refresh operation and an external circuit associated therewith. Thus, the random access memory of this arrangement constructs, in effect, a pseudo static random access memory.
U.S. Pat. No. 4,376,989 issued Mar. 15, 1983 to Takemae, entitled "Semiconductor Dynamic Memory", describes a DRAM including a plurality of functional blocks or interface circuits for controlling the memory, such as a row-enable buffer, a row-address buffer, a word decoder, a column-enable buffer, a column-address buffer, and a column decoder. The functional blocks in the DRAM are sequentially reset by signals from the subsequent functional block so that the power operations of the functional blocks of the subsequent stages is indicated by the reset signal, and thus are returned to the state in which they are ready to execute the next processing.
U.S. Pat. No. 4,618,947 issued Oct. 21, 1986 to Tran et al., entitled "Dynamic Memory With Improved Address Counter For Serial Modes", discloses a DRAM that has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column address is latched when a serial mode is initiated, and the counter steps through the programmed number of bits, starting at the initial address. The number of bits used in the serial mode may be selected by metal-mask programming. To avoid a speed penalty, look-ahead circuitry initiates the set up for serial mode before the controls for this mode are detected.
U.S. Pat. No. 4,725,945 issued Feb. 16, 1988 to Kronstadt et al., entitled "Distributed Cache In Dynamic Rams", discloses a microcomputer memory system that is organized into a plurality of banks. Each bank consists of an array of static column mode, DRAMS of the type having an on-chip static buffer for storing an entire row. The static buffers associated with each bank function as a distributed cache to hold the last accessed row for the associated bank. A memory controller receives real addresses from a CPU or other device on the memory bus and extracts bank and row numbers from the address. The memory controller determines whether the accessed row for a memory bank is in the distributed cache and, if it is, accesses the distributed cache for that bank. Otherwise, the memory controller switches the contents of the distributed cache with the contents of the addressed row for that bank.
U.S. Pat. No. 4,722,074 issued Jan. 26, 1988 to Fujishima et al., entitled "Semiconductor Storage Unit With I/O Bus Precharging and Equalization", describes a first precharging and equalizing circuit that precharges and equalizes I/O buses in advance to selection of bit lines, and following thereto, a second precharging and equalizing circuit precharges and equalizes the I/O buses during driving operation of a sense amplifier. Thus, potential levels of the I/O buses are prevented from being changed by vibration of the output level of the sense amplifier transmitted to the I/O buses through parasitic capacitance during driving operation of the sense amplifier.
U.S. Pat. No. 4,754,433 issued Jun. 28, 1988 to Chin et al., entitled "Dynamic RAM having Multiplexed Twin I/O Line Pairs", describes a DRAM including a first and second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation, the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation, a high speed dual bit per CAS cycle page mode is achieved wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation, data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.
U.S. Pat. No. 4,800,531 issued Jan. 24, 1989 to Dehganpour et al., entitled "Address Buffer Circuit For A DRAM", discloses a DRAM that has an input address buffer in which the first stage is a NOR gate. The output of the NOR gate is clocked to a latch which is preset to the slow condition of the NOR gate. The NOR gate is clocked separately from the clocking of the output of the NOR gate to the latch. A refresh control circuit has an output which is also clocked to the latch. The latch provides an internal address signal for selecting a word line. The internal address signal is representative of the output of the NOR gate when the DRAM is running a data cycle and is representative of the output of the refresh control circuit when the DRAM is running a refresh cycle.
U.S. Pat. No. 4,758,987 issued Jul. 19, 1988 to Sakui, entitled "Dynamic Semiconductor Memory With Static Data Storing Cell Unit", discloses a dynamic random access memory wherein memory cell word lines are provided substantially perpendicular to bit lines. Memory cells are provided at intersections of the bit lines and the memory cell word lines. Sense-amplifiers are connected to the bit line pair. Static memory cells are also connected to the bit lines and serve as an auxiliary memory. When a memory cell word line is selected, the static memory cells statically hold data voltages stored in an array of memory cells connected to the selected word line until another word line is selected. Thus, during a precharge period of the bit lines, the data voltages can be stored in the static memory cells. Therefore, even during the precharge period, data read/write is enabled.
Japanese Patent 60-211696 issued Oct. 24, 1985 to Miyazawa, entitled "Dynamic Ram", relates to a technique for reading a dynamic RAM at a high speed by lowering slightly a precharge level by means of a level adjusting circuit while synchronizing a selection action of a memory cell.
Japanese Patent 61-230697 issued Oct. 14, 1986 to Miyatake, entitled "Dynamic Semiconductor Memory Device", relates to a technique to shorten the access time and to attain a high-speed operation of a dynamic semiconductor memory device by lowering the precharging level of an address decoder circuit down to about half of the power supply voltage.
Japanese Patent 61-222089 issued Oct. 2, 1986 to Watanabe, entitled "Equalizing and Precharging Circuit", relates to a method and circuit to shorten access time and to stabilize reading operation by using a MOSFET for precharging in time division an active load having high resistance.
Japanese Patent 61-126683 issued Jun. 14, 1986 to Aono, entitled "Semiconductor Memory Device", discloses a circuit to decrease a delay due to a precharging and to make an action highly speedy by precharging a bit line with plural electric current paths.
European Patent Application no. 80101777.3 filed Apr. 3, 1980 by Shoji and published Oct. 29, 1980 discloses a memory device operable at high-speed and with low power consumption. In this device row address information and column address information are incorporated in synchronism with a row strobe signal and a column strobe signal, respectively, and refresh is effected in response to a row address. The device comprises a plurality of groups of selection gates for selectively supplying the incorporated column address information to a part of a plurality of column address decoders.
A publication in the IBM Technical Disclosure Bulletin, Vol. 31, No. 2, July 1988 at page 24, entitled "Early Read of Dynamic RAM in an Intel 80286 Microprocessor-Based System", describes a technique utilizing early read of DRAM in an Intel 80286 microprocessor-based system to eliminate the need for additional wait states during memory reads.
Accordingly, it is an object of this invention to provide a system which enables an extended reset/precharge time for a DRAM.
It is another object of this invention to provide a system for relaxing DRAM RAS reset/precharge times without requiring an alteration of the CPU generated RAS signal.
It is still another object of this invention to provide a system for relaxing a DRAM RAS reset/precharge time while providing a more accurate reset/precharge time than was heretofore available.